Capacitors are one type of component which is commonly used in the fabrication of integrated circuits, for example in DRAM circuitry. A typical capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric region. As integrated circuitry density has increased, there is a continuing challenge to maintain sufficiently high storage capacitance despite typical decreasing capacitor area. The increase in density of integrated circuitry has typically resulted in greater reduction in the horizontal dimension of capacitors as compared the vertical dimension. In many instances, the vertical dimension of capacitors has increased.
One manner of forming capacitors is to initially form an insulative material within which a capacitor storage node electrode is formed. For example, an array of capacitor electrode openings for individual capacitors is typically fabricated in such insulative capacitor electrode-forming material, with a typical insulative electrode-forming material being silicon dioxide doped with one or both of phosphorus and boron. The capacitor electrode openings are typically formed by etching. However, it can be difficult to etch the capacitor electrode openings within the insulative material, particularly where the openings are deep.
Further and regardless, it is often desirable to etch away most if not all of the capacitor electrode-forming material after individual capacitor electrodes have been formed within the openings. Such enables outer sidewall surfaces of the electrodes to provide increased area, and thereby increased capacitance for the capacitors being formed. However, the capacitor electrodes formed in deep openings are typically correspondingly much taller than they are wide. This can lead to toppling of the capacitor electrodes either during the etch to expose the outer sidewall surfaces, during transport of the substrate, and/or during deposition of the capacitor dielectric layer or outer capacitor electrode layer. Our U.S. Pat. No. 6,667,502 teaches provision of a brace or retaining structure intended to alleviate such toppling.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents. the capacitor electrode outer sidewalls are incorporated into a plurality of capacitors.
In one implementation, a pair of adjacent capacitors includes a substrate comprising substantially vertically oriented inner capacitor electrodes having respective elevationally outermost and elevationally innermost surfaces. The inner capacitor electrodes have outer sidewalls. An electrically insulative ring is received laterally about each of the inner capacitor electrode outer sidewalls at some common substrate elevation intermediate said outermost and innermost surfaces. The insulative rings are spaced from one another. A capacitor dielectric layer is received over each of the insulative rings and over the inner capacitor electrodes. An outer capacitor electrode is received over each of the insulative rings and over the capacitor dielectric layer.
In one implementation, a pair of adjacent capacitors includes a substrate comprising substantially vertically oriented inner capacitor electrodes having respective elevationally outermost and elevationally innermost surfaces. The inner capacitor electrodes have outer sidewalls. An electrically insulative ring is received laterally about each of the inner capacitor electrode outer sidewalls at some common substrate elevation intermediate said outermost and innermost surfaces. The insulative rings each have a laterally peripheral surface. Such peripheral surfaces of each ring touch one another intermediate the pair of adjacent capacitors. A capacitor dielectric layer is received over each of the insulative rings and over the inner capacitor electrodes. An outer capacitor electrode is received over each of the insulative rings and over the capacitor dielectric layer.
Other aspects and implementations are contemplated.